Silicon

Reviews

• (Solicited Review) “Fracture strength of micro- and nano-scale silicon components,” F.W. DelRio, R.F. Cook, and B.L. Boyce, Appl. Phys. Rev. 2 (2015) 021303-1-51. (Editors Pick for 2015.)
• (Invited Review) “Strength and Sharp Contact Fracture of Silicon,” R.F. Cook, J. Mat. Sci. 41 Special 40th Anniversary Issue (2006) 841-872.

Key Works

• “Stress-Corrosion Cracking in Silicon,” M.D. Thouless and R.F. Cook, Appl. Phys. Letters 56 (1990) 1962-1964.
• “Indentation Induced Amorphization and Conductivity of Silicon and Germanium,” D.R. Clarke, C.M. Kroll, P.D. Kirchner, R.F. Cook and B.J. Hockey, Phys. Rev. Letters 60 (1988) 2156-2159.

Topical Works

• “In situ observations of Berkovich indentation induced phase transitions in crystalline silicon films,” Y.B. Gerbig, C.A. Michaels, and R.F. Cook, Scripta Mater. 120 (2016) 19-22.
• “In situ observation of the spatial distribution of crystalline phases during pressure-induced transformations of indented silicon thin films,” Y.B. Gerbig, C.A. Michaels, and R.F. Cook, J. Mater. Res. 30 (2015) 390-406.
• “In situ spectroscopic study of the plastic deformation of amorphous silicon under non-hydrostatic conditions induced by indentation,” Y.B. Gerbig, C.A. Michaels, J.E. Bradby, B. Haberl, and R.F. Cook, Phys. Rev. B 92 (2015) 214110-1-15.
• “Roughness scaling of deep reactive ion etched silicon surfaces,” F.W. DelRio, L.H. Friedman, W.A. Osborn, M.S. Gaither, and R.F. Cook, J. Appl. Phys. 114 (2013) 113506-1-6.
• “In situ observation of the indentation-induced phase transformation of silicon thin films,” Y.B. Gerbig, C.A. Michaels, A.M. Forster, and R.F. Cook, Phys. Rev. B 85 (2012) 104102.
• “Direct observation of phase transformation anisotropy in indented silicon studied by confocal Raman spectroscopy,” Y.B. Gerbig, S.J. Stranick, and R.F. Cook, Phys. Rev. B. 83 (2011) 205209-1-5.
• “Measurement of residual stress field anisotropy at indentations in silicon,” Y.B. Gerbig, S.J. Stranick, and R.F. Cook, Scripta Mater. 63 (2010) 512-515.
• “Effect of crystallographic orientation on phase transformations during indentation of silicon,” Y.B Gerbig, S.J. Stranick, D.J. Morris, M.D. Vaudin, and R.F. Cook, J. Mater. Res., 24 (2009) 1172-1183.
• “Giant pop-ins in nanoindented silicon and germanium caused by lateral cracking,” D.J. Oliver, B.R. Lawn, R.F. Cook, M.G. Reitsma, J.E. Bradby, J.S. Williams, and P. Munroe, J. Mater. Res. 23 (2008) 297-301
• “Stable Dielectric Fracture at Interconnects from Electromigration Stresses,” J. Thurn and R.F. Cook, Acta Mater. 50 (2002) 2627-2637.
• “Electrical Resistance of Metallic Contacts on Silicon and Germanium during Indentation,” G.M. Pharr, W.C. Oliver, R.F. Cook, P.D. Kirchner, M.C. Kroll, T.R. Dinger, and D.R. Clarke, J. Mat. Res. 7 (1992) 961-972.
• “Method and Apparatus for Preventing Chip Breakage During Semiconductor Manufacturing Using Wafer Grinding Striation Information,” R.L. Mendelson, R.F. Cook, D.F. Diefenderfer and E.G. Liniger, United States Patent, 5,888,838 (March, 1999).
• “Chip Crack Stop,” R.L. Mendelson, R.F. Cook, E.G. Liniger and R.C. Whiteside, United States Patent, 6,022,791 (February, 2000)
• “Integrated Circuit having Crack Stop for Interlevel Dielectric Layers,” R.F. Cook, E. Garcia, N.A. Greco, S.E. Greco and E.N. Levine, United States Patent, 6,091,131 (July, 2000).
• “Method and Apparatus for Preventing Chip Breakage During Semiconductor Manufacturing Using Wafer Grinding Striation Information,” R.L. Mendelson, R.F. Cook, D.F. Diefenderfer and E.G. Liniger, United States Patent 6,171,873 B1 (January, 2001).
• “Method for Producing a Crack Stop for Interlevel Dielectric Structures,” R.F. Cook, E. Garcia, N.A. Greco, S.E. Greco and E.N. Levine, United States Patent, 6,174,814 B1 (January, 2001).
• “Mechanical Strength Die Sorting,” R.F. Cook, R.L. Mendelson, E.G. Liniger and D.R. Sanders, United States Patent 6,222,145 (April, 2001).
• “Method and System for Dicing Wafers, and Semiconductor Structures Incorporating the Products Thereof,” T.G. Ference, R.L. Mendelson, R.F. Cook, E.G. Liniger, D.W. Brouillete and W.J. Howell, United States Patent 6,271,102 B1 (August, 2001)
• “Semiconductor structure and package including a chip having chamfered edges,” D.W. Brouillette, R.F. Cook, T.G. Ference, W.J. Howell, E.G. Liniger and R.L. Mendelson, United States Patent, 6,600,213 (July 2003)
• “Method and system for dicing wafers, and semiconductor structures incorporating the products thereof,” D.W. Brouillette, R.F. Cook, T.G. Ference, W.J. Howell, E.G. Liniger and R.L. Mendelson, United States Patent, 6,915,795 (July 2005)